Silicon resonant tunneling

ABSTRACT

A resonant tunneling diode (400) made of a silicon quantum well (406) with silicon oxide tunneling barriers (404, 408). The tunneling barriers have openings (430) of size smaller than the electron wave packet spread to insure crystal alignment through the diode without affecting the tunneling barrier height.

BACKGROUND OF THE INVENTION

The invention relates to electronic devices, and, more particularly, toresonant tunneling devices and systems.

The continual demand for enhanced transistor and integrated circuitperformance has resulted in improvements in existing devices, such assilicon bipolar and CMOS transistors and gallium arsenide MESFETs, andalso in the introduction of new device types and materials. Inparticular, scaling down device sizes to enhance high frequencyperformance leads to observable quantum mechanical effects such ascarrier tunneling through potential barriers. This led to development ofalternative device structures such as resonant tunneling diodes andresonant tunneling hot electron transistors which take advantage of suchtunneling phenomena.

Resonant tunneling diodes are two terminal devices with conductioncarriers tunneling through potential barriers to yield current-voltagecurves with portions exhibiting negative differential resistance. Recallthat the original Esaki diode had interband tunneling (e.g., fromconduction band to valence band) in a heavily doped PN junction diode.An alternative resonant tunneling diode structure relies on resonanttunneling through a quantum well in a single band; see FIG. 1 whichillustrates a AlGaAs/GaAs quantum well. Further, Mars et al.,Reproducible Growth and Application of AlAs/GaAs Double Barrier ResonantTunneling Diodes, 11 J.Vac.Sci.Tech.B 965 (1993), and Ozbay et al,110-GHz Monolithic Resonant-Tunneling-Diode Trigger Circuit, 12 IEEEElec.Dev.Lett. 480 (1991), each use two AlAs tunneling barriers imbeddedin a GaAs structure to form a quantum well resonant tunneling diode. Thequantum well may be 4.5 nm thick with 1.7 nm thick tunneling barriers.FIG. 2 illustrates current-voltage behavior at room temperature. Notethat such resonant tunneling "diodes" are symmetrical. With the biasshown in FIG. 3a, a discrete electron level (bottom edge of a subband)in the quantum well aligns with the cathode conduction band edge, soelectron tunneling readily occurs and the current is large. Contrarily,with the bias shown in FIG. 3b the cathode conduction band alignsbetween quantum well levels and suppresses tunneling, and the current issmall.

Attempts to fabricate quantum wells in silicon-based semiconductors,rather than the III-V semiconductors such as AlGaAs and GaAs, havefocussed primarily on silicon-germanium alloys. For example, the TopicalConference on Silicon-Based Heterostructures II (Chicago 1992) includedpapers such as Grutzmacher et al., Very Narrow SiGe/Si Quantum WellsDeposited by Low-Temperature Atmospheric Pressure Chemical VaporDeposition, 11 J.Vac.Sci.Tech.B 1083 (1993)(1 nm wide wells of Si₀.75Ge₀.25 with 10 nm wide Si tunneling barriers) and Sedgwick et al.,Selective SiGe and Heavily As Doped Si Deposited at Low Temperature byAtmospheric Pressure Chemical Vapor Deposition, 11 J.Vac.Sci.Tech.B 1124(1993)(Si/SiGe resonant tunneling diode selectively grown in an oxidewindow with silicon tunneling barriers each 5 nm wide and a 6 nm widequantum well of Si₀.75 Ge₀.25. Because the valence band offset greatlyexceeds the conduction band offset at SiGe/Si interfaces, mostinvestigators consider hole tunneling rather than electron tunnelingusing strained layer SiGe.

However, SiGe strained layers possess a serious intrinsic impediment inthat the band discontinuities are small (less than 500 meV). Thisprecludes room temperature operation with large peak-to-valley currentdifferences (greater than approximately 5). Further, the addition of astrained heterojunction and new material, germanium, necessitates theundesirable development and implementation of new low temperaturefabrication methods to allow production.

Tsu, U.S. Pat. No. 5,216,262, describes a silicon-based quantum wellstructure with tunneling barriers made of short period silicon/silicondioxide superlattices of epitaxial silicon dioxide two monolayers thick.

Numerous investigators have studied the silicon/silicon oxide interfacebecause it underlies performance of the currently prevalent CMOStransistor structure of silicon integrated circuits. The growth andanalysis of single molecular layers of oxide have become commonplace.For example, Ohmi et al., Very Thin Oxide Film on a Silicon Surface byUltraclean Oxidation, 60 Appl.Phys.Lett. 2126 (1992); Hattori, HighResolution X-ray Photoemission Spectroscopy Studies of Thin SiO₂ andSi/SiO₂ Interfaces, 11 J.Vac.Sci.Tech.B 1528 (1993); and Seiple et al.,Elevated Temperature Oxidation and Etching of the Si(111) 7×7 SurfaceObserved with Scanning Tunneling Microscopy, 11 J.Vac.Sci.Tech.A 1649(1993). The Ohmi et al. article observes that an oxide monolayer formedon a silicon wafer at 300° C. provides the foundation for oxide filmssuperior to standard thermal oxide with respect to Frenkel-Pooleemission for thin oxide films.

SUMMARY OF THE INVENTION

The present invention provides silicon-based resonant tunneling diodesand transistors by use of perforated silicon dioxide tunneling barriersfor epitaxial alignment of anode, cathode, and quantum well siliconlayers.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings are schematic for clarity.

FIGS. 1-3b are band diagrams of a known resonant tunneling diodetogether with a current-voltage diagram.

FIGS. 4a-d illustrate a first embodiment diode in cross sectionalelevation and alternative plan views.

FIGS. 5a-c are band diagrams for the first preferred embodiment diodewith various biases.

FIGS. 6a-e show fabrication steps of the first preferred embodimentdiode.

FIGS. 7-8 illustrate other preferred embodiment diodes.

FIGS. 9-11 show a memory cell application of the preferred embodimentdiodes.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First preferred embodiment resonant tunneling diode FIGS. 4a-bheuristically show first preferred embodiment resonant tunneling diode,generally denoted by reference numeral 400, in cross sectional elevationand plan views as including silicon anode 402, silicon dioxide ("oxide")tunneling barrier 404, silicon quantum well 406, oxide tunneling barrier408, silicon cathode 410, anode metal contact 422, and cathode metalcontact 420. Tunneling barriers 404 and 408 each has the structure of agrid with a period of about 20 nm and a separation less thanapproximately 4 nm in grid openings 430. The plan view in FIG. 4billustrates the grid structure of each of the tunneling barriers404/408. Tunneling barriers 404/408 are each about 1 nm thick (roughly 4molecular layers and amorphous) with transition layers and about 1 μm by2 μm (thus FIGS. 4a-b are not to scale in that there should be roughly50 rows of 100 openings 430 in each tunneling barrier, and not the 5rows of 9 openings illustrated in FIG. 4b). Quantum well 406 is about 4nm thick. Note that the thickness of barriers 404/408 primarily impactsthe tunneling current magnitude and not the resonance levels whichderives from the quantum well width and the barrier heights. Also, theexact electronic and chemical nature of the tunneling barriers variesthrough the barrier.

The spread of a wave packet describing an electron in a periodicpotential (i.e., an electron in the single crystal silicon of anode 402,quantum well 406, or cathode 410) is roughly the reciprocal of thespread of wave vectors making up the wave packet. Thus with a spread ofwave vectors small compared to dimensions of the Brillouin zone (whichwould be required for any resonance with respect to wave vector), thewave packet spread is over many crystal primitive cells. The wave packetspread in silicon is at least roughly 4 nm or more than 7 primitivecells. Each of openings 430 in the tunneling barrier oxides has adiameter of at most 4 nm and may be smaller. Hence, tunneling barriers404/408 will appear to electrons (wave packets) as continuous andwithout penetrable openings.

The width of quantum well 406 as 4 nm implies the edges of the lowestconduction subbands should lie at about 20 meV, 85 meV, 200 meV, and 350meV above the conduction band edge due to the quantized component ofcrystal momentum in the quantum well. The conduction band offset at thesilicon/oxide interface for very thin oxide is about 2.9 eV (comparedwith 3.2 eV for thick oxide), so FIG. 5a-c represents the band diagramfor electron conduction through diode 400. In FIG. 5a a zero biasproduces no current; in FIG. 5b a bias of approximately 100 mV acrossdiode 400 yields the first resonant peak current; and in FIG. 5c a biasof approximately 150 mV across diode 400 leads to the first valleycurrent. Note that anode 402 may be doped n+ except for a few nmabutting barrier 404, and cathode 410 may be also be doped n+ except fora few nm abutting barrier 408. Spacing the doping from the tunnelingbarriers avoids incorporating dopant atoms into the tunneling barrierand grid spacing regions where impurity-assisted tunneling can result.With a doped anode and cathode, the majority of the applied bias betweenanode and cathode appears across the barriers and quantum well. Thedielectric constant of silicon is about three times that of oxide, sothe applied voltage drop roughly splits into one third across the oxidebarriers, one third across the quantum well, and one third across theundoped anode and cathode abutting the oxide barriers. The breakdownvoltage for oxide is on the order of 10 MV/cm, so to avoid breakdowncurrents which may destroy the oxide barriers, voltage drops must beless than about 3 volts across the entire double barrier neglectingdepletion on the cathode side of the tunneling barriers.

FIG. 4c shows in plan view an alternative set of openings 440 intunneling barrier oxides 404 and 408. The alternative openings 440 areparallel 4 nm wide slots which separate regions of tunneling barrieroxide. The orientation of openings may be arbitrary. As long as at leastone dimension of the openings is less than about 4 nm, the tunnelingbarrier will be a barrier.

Similarly, FIG. 4d shows in plan view a further alternative openings 470in tunneling barrier oxides 404 and 408. The alternative opening 470 isa 4 nm wide net which separates the tunneling barrier oxide into anarray of hexagons. The orientation of openings may be arbitrary. As longas at least one dimension of the openings is less than about 4 nm, thetunneling barrier will be a barrier. Also, the extensive area for thesilicon epitaxial growth may simplify the epitaxy.

Diode 400 thus provides resonant tunneling in a system using onlystandard integrated circuit materials: silicon and oxide; and mayoperate at room temperature.

Fabrication

FIGS. 6a-e illustrate in cross sectional elevation views a firstpreferred embodiment method of fabrication of diode 400 which includesthe following steps:

(a) Begin with 25-mil thick, four-inch diameter, (100)-oriented siliconwafer 600. Epitaxially grow 1 μm thick n+ layer of silicon 602 on wafer600 in an LPCVD (low pressure chemical vapor deposition) reactor bydecomposition of dichlorosilane with stibine (SbH₃) for in situ antimonydoping. Next, clean wafer 600 by first rinsing in an HF/NH₄ F solutionto remove the roughly 1.4 nm of native oxide which grows when wafer 600contacts air and then rinsing with deionized water. The HF/NH₄ F rinsestabilizes the oxide-free silicon surface by forming a monohydridesurface layer. Next, insert wafer 600 into a molecular beam epitaxy(MBE) growth chamber and desorb the hydrogen, and then grow 7 nm ofundoped epitaxial silicon 604 at about 500° C. Remove wafer 600 from theMBE growth chamber and again perform the HF/NH₄ F plus water cleaningwhich will leave about 6 nm of undoped hydride stabilized silicon 604.Next, insert wafer 600 into a furnace and heat it to 300° C. in anoxygen free argon atmosphere, and then oxidize wafer 600 at 300° C. in amoisture free oxygen atmosphere. This desorbs the hydrogen and grows amonolayer of oxide. A greater thickness of oxide is desired, so afterthe oxide monolayer growth, heat the wafer to a growth temperature of900° C. in oxygen free argon, and then inject sufficient oxygen to growabout 3 nm of oxide 606. See FIG. 6a.

(b) Insert wafer 600 into an ion beam lithography machine, and use abeam of protons (hydrogen ions) at 20 KeV to remove oxide in 4 nmdiameter openings from oxide 606 in a grid pattern. Focus the ion beamto a spot size of less than 4 nm, and raster scan the ion beam acrosswafer 600. Note that the beam need not be aligned to anything and just apattern of about 4 nm diameter openings need be produced. The lowpressure within an ion beam machine will desorb roughly one monolayer ofoxide 606 in the form of SiO from areas not sputtered away. In effect,about a monolayer of SiO may be lost due to evaporation in the lowpressure; the oxide openings will form by oxygen and silicon atoms beingsputtered away; and some silicon beneath the sputtered oxide will alsobe sputtered away or removed by formation of water vapor. The crystaldamage will not be severe due to the low beam energy, and a latertemperature cycle will anneal out the damage. See FIG. 6b whichindicates crystal damage with wavy lines.

(c) Remove wafer 600 from the ion beam machine and again clean with theHF/NH₄ F plus water rinses to remove native oxide which grows on thesilicon exposed by the openings in oxide 606. This also removes about 2nm of oxide 606, leaving just a little more than the desired less than 1nm thick tunneling barrier. Again, the HF/NH₄ F rinse stabilizes theoxide-free silicon surface exposed by the openings in oxide 606 throughformation of a hydride monolayer. Then insert wafer 600 into a molecularbeam epitaxy (MBE) growth chamber and desorb the hydrogen and anneal theion beam crystal damage with a short temperature cycle up to 800° C. andthen grow undoped epitaxial silicon 608 at 500° C. The short hightemperature cycle anneals out the residual crystal damage withoutsignificantly evaporating oxide; the usual MBE native oxide desorptionemploys 1000°-1250° C. The epitaxial growth begins on the exposedsilicon in the oxide openings and eventually spreads laterally acrossoxide 606. Continue growth until silicon 608 is 6 nm thick on oxide 606.Remove wafer 600 from the MBE growth chamber and again apply the HF/NH₄F plus water rinse cleanup to remove the native oxide and yield astabilized oxide-free hydrided silicon surface. See FIG. 6c.

(d) Again insert wafer 600 into a furnace and heat it to 300° C. in anoxygen free argon atmosphere, and then oxidize wafer 600 at 300° C. in amoisture free oxygen atmosphere to grow a monolayer of oxide. After theoxide monolayer growth, heat the wafer to a growth temperature of 900°C. in oxygen free argon, and then inject sufficient oxygen to grow about3 nm of oxide 610. Then repeat step (b) to form a grid of 4 nm diameteropenings in oxide 610 by ion beam sputtering. This grid need not bealigned to the grid from step (b) and may in fact have a differentperiod. See FIG. 6d.

(e) Lastly, repeat step (c) but grow only 6 nm of silicon 612 on oxide610. Then by LPCVD epitaxially grow 200 mm of in situ doped silicon bydecomposition of dichlorosilance plus stibine. Thenphotolithographically pattern and mesa etch with a fluorine based etchplus deposit anode and cathode contact metal to complete the diode; seeFIG. 6e.

Note that the ion beam lithography could be incorporated into the MBEmachine and thereby avoid some of the wafer transfer operations. In sucha case, the ion beam could be used for silicon surface cleaning.Further, oxide growth could be performed within the MBE machine by usingbeams of both silicon and oxygen as suggested in the Tsu patent cited inthe background, although the lattice matched oxide of Tsu is notrequired in the preferred embodiments.

Second preferred embodiment

FIG. 7 heuristically illustrates in cross sectional elevation viewsecond preferred embodiment silicon/oxide resonant tunneling diode 700which differs from diode 400 by having the 4 nm diameter openings 730 inoxide tunneling barriers 704 and 708 spaced about 1 μm apart rather thanthe 16 nm apart of diode 400. Again the openings in the oxide tunnelingbarriers are small enough to prevent electrons from passing through butstill provide a crystal alignment mechanism for insuring epitaxialgrowth of quantum well 706 and anode 702. The fabrication of diode 700follows that of diode 400; however, the epitaxial silicon growth mayrequire a higher growth temperature (e.g., 800° C.) or rapid thermalannealing (xenon flash lamps) or both to insure the single crystalcharacter of the silicon epilayers. Indeed, if the spacing betweenopenings exceeds the diameter of the diode, then the mesa etch caneliminate the openings and provide uninterrupted oxide tunnelingbarriers. In this case the oxide openings need not be of diameter lessthan 10 nm and could in fact be a wide ring encircling the eventualtunneling barrier. The ease of lateral recrystallization of the roughly6 nm thick quantum well silicon layer will determine the diode diameter.Of course, thicker silicon could be grown and etched back in variousways, such as by cycles of native oxide growth and removal.

Third preferred embodiment

FIG. 8 heuristically illustrates in cross sectional elevation view thirdpreferred embodiment silicon/oxide resonant tunneling diode 800 whichdiffers from diodes 400 and 700 by having oxide isolation rather thanmesa isolation. Indeed, diode 800 may be fabricated along the lines ofeither diode 400 or diode 700 with replacement of the final mesa etchingreplaced by a masked thermal oxidation or oxygen implantation to formisolation oxide 850. Otherwise, oxide tunneling barriers 804/808 andsilicon quantum well 806 plus silicon anode 802 and cathode 810 have thesame characteristics as the corresponding parts of either diode 400 ordiode 700.

Multipeak resonances

The preferred embodiments may be extended to multiple quantum wells inseries to form resonant tunneling diodes with multiple resonant peakssimply be growing further tunneling barriers and quantum wells on thepreferred embodiment structures. Indeed, with successive abuttingquantum wells and tunneling barriers grown, a superlattice structure maybe obtained analgous to that of the Tsu patent cited in the background.

Applications

The preferred embodiments diodes may be incorporated into variousstructures such as the memory cell illustrated in FIGS. 9-11. Inparticular, FIG. 9 schematically shows static random access memory(SRAM) cell 900 as including resonant tunneling diodes 902 and 904 inseries (RTD 902 acts as the load for RTD 904) and coupled to bitline 910by silicon field effect transistor pass gate 908 controlled by thevoltage on word line 912. The bistability of node 906 of cell 900derives from the bias voltage Vdd being set a little greater than thecurrent valley of each RTD, so one RTD operates in its valley and theother RTD operates with small bias. FIG. 10 shows the superimposedcurrent-voltage curves for RTDs 902-904 where each RTD has thecharacteristics illustrated in FIG. 2. The intersection points (a pairfor the voltage on node 906 close to Vdd (high) and a pair for node 906low) indicate the stable series operation points. And accessing node 906through pass gate 908 with a large driver to force node 906 either highor low will force cell 900 into a desired stable state; whereas, a senseamplifier accessing node 906 through pass gate 908 will detect thecell's state without disruption. Of course, a larger peak-to-valleyratio in the RTDs than that shown in FIG. 2 will make the high and lowstable voltages for node 906 closer to Vdd and 0, respectively.

FIG. 11 illustrates in perspective view the structure of FIG. 9 using asingle silicon field effect transistor plus the preferred embodimentRTDs. Note that the parallel arrangement of the RTDs on the field effecttransistor drain permits simultaneous fabrication with a mesa etchdefining the locations of the RTDs.

Epitaxial tunneling barrier

The preferred embodiments may also be applied to epitaxial tunnelingbarriers, such as the two monolayer, strained layer oxide of the Tsupatent cited in the background and calcium fluoride (CaF₂) and zincsulfide (ZnS) tunneling barriers which are latticed matched to silicon.Indeed, the use of openings for epitaxial growth of silicon through andonto the other side of a tunneling barrier layer will insure goodlattice match of this grown silicon for both latticed matched layers andnonlatticed matched layers. A recrystallization anneal may be requiredto eliminate crystal defects such as may arise from silicon nucleationon the barrier layer which is independent of the growth through theopenings. A high growth temperature will likely lessen the anneal need.

In general, any crystalline material could be substituted for siliconand any other material for the tunneling barrier layer material, and thepreferred embodiment approach of forming openings in the tunnelingbarrier layer to extend the crystalline material epitaxial growth willstill apply. Further, the tunneling barriers could be superlattices asin Tsu, and multiple diodes could be formed in stacks or in parallel andinserted into emitters of bipolar or hot electron transistors. Lastly,the epitaxial material may be changed during each overgrowth so that thequantum well material could differ from the anode and cathode materialsand still be lattice matched (or strained to match).

Modifications and advantages

The preferred embodiments may be varied in many ways while retaining oneor more of the features of epitaxial alignment of anode, cathode, andquantum well layers by openings in barrier layers for epitaxial growthand such resonant tunneling heterostructures.

For example, the dimensions and grid patterns could be varied providedno openings with too large a diameter appear, for instance, the twotunneling barriers could have different patterns, the patterns couldchange within a single tunneling barrier, the tunneling carrier could beholes rather than electrons. The ion beam removal of oxide to form thetunneling barrier grids could be inert gas ions such as helium, neon,argon, krypton, or xenon which would provide a larger mass ion forselectable momentum transfer efficiency and still yield neutral productswhich evaporate. Heterojunction bipolar transistors with resonanttunneling diodes imbedded in the emitters and with silicon-germaniumbases or homojunctions bipolar transistors with resonant tunnelingdiodes imbedded in the emitters may be fabricated.

The tunneling barrier oxide openings to insure epitaxial silicon has theadvantage of providing resonant tunneling structures in the standardsilicon/oxide materials system. And in transistors and circuits theresonant tunneling structures have an advantage of increasing the amountof logic or memory performed per unit area. For example, resonanttunneling bipolar transistors consisting of resonant tunneling elementsin the emitter of conventional bipolar transistors have been used toconstruct full adder circuits with one third the usual number oftransistors and one third the gate delay of conventional technology.

What is claimed is:
 1. A resonant tunneling diode, comprising:(a) afirst terminal, a second terminal, and a quantum well; and (b) first andsecond tunneling barriers, said first tunneling barrier separating saidquantum well from said first terminal and said second tunneling barrierseparating said quantum well from said second terminal, said firsttunneling barrier including a region of material having the same bandgapas at least one of said first terminal and said quantum well and whichabuts both said quantum well and said first terminal and also includinga second region of material having a bandgap larger than at least one ofsaid first terminal and said quantum well.
 2. The diode of claim 1,wherein:(a) said first terminal, said second terminal, and said quantumwell are made of silicon; and (b) said first tunneling barrier and saidsecond tunneling barrier include a compound of silicon and oxygen. 3.The diode of claim 1, wherein:(a) said region has a grid pattern.
 4. Thediode of claim 2, wherein:(a) said compound is silicon dioxide.
 5. Anintegrated circuit, comprising:(a) a silicon-based transistor; and (b) asilicon resonant tunneling diode with tunneling barriers including anamorphous silicon-oxygen compound, said diode coupled to saidtransistor.
 6. The integrated circuit of claim 5, wherein:(a) saidtunneling barriers each includes a region of silicon which abuts siliconregions on both sides of one of said tunneling barriers.
 7. Theintegrated circuit of claim 6, wherein:(a) said region of silicon has agrid pattern.
 8. The integrated circuit of claim 5, wherein:(a) saidsilicon-oxygen compound is silicon dioxide.
 9. The integrated circuit ofclaim 5, wherein:(a) said transistor is an insulated gate field effecttransistor.